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| HY29DS322/HY29DS323 32 Megabit (4M x 8/2M x16) Super-Low Voltage, Dual Bank, Simultaneous Read/Write, Flash Memory KEY FEATURES n Single Power Supply Operation n n n n n n n n n n n - Read, program, and erase operations from 1.8 to 2.2 V (2.0V 10%) - Ideal for battery-powered applications Simultaneous Read/Write Operations - Host system can program or erase in one bank while simultaneously reading from any sector in the other bank with zero latency between read and write operations High Performance - 100, 110 and 120 ns access time versions Ultra Low Power Consumption (Typical Values) - Automatic sleep mode current: 5 A - Standby mode current: 5 A - Read current: 5 mA (at 5 MHz) - Program/erase current: 20 mA Boot-Block Sector Architecture with 71 Sectors in Two Banks for Fast In-System Code Changes Secured Sector: An Extra 64 Kbyte Sector that Can Be: - Factory locked and identifiable: 16 bytes available for a secure, random factory Electronic Serial Number - Customer lockable: Can be read, programmed, or erased just like other sectors Flexible Sector Architecture - Sector Protection allows locking of a sector or sectors to prevent program or erase operations within that sector - Temporary Sector Unprotect allows changes in locked sectors (requires high voltage on RESET# pin) Automatic Erase Algorithm Erases Any Combination of Sectors or the Entire Chip Automatic Program Algorithm Writes and Verifies Data at Specified Addresses Compliant with Common Flash Memory Interface (CFI) Specification Minimum 100,000 Write Cycles per Byte/ Word Compatible with JEDEC Standards - Pinout and software compatible with single-power supply Flash devices - Superior inadvertent write protection n Data# Polling and Toggle Bits n n n n n n - Provide software confirmation of completion of program or erase operations Ready/Busy# Pin - Provides hardware confirmation of completion of program or erase operations Erase Suspend - Suspends an erase operation to allow programming data to or reading data from a sector in the same bank - Erase Resume can then be invoked to complete the suspended erasure Hardware Reset Pin (RESET#) Resets the Device to Reading Array Data WP#/ACC Input Pin - Write protect (WP#) function allows hardware protection of two outermost boot sectors, regardless of sector protect status - Acceleration (ACC) function provides accelerated program times Fast Program and Erase Times - Sector erase time: 2 sec typical - Byte/Word program time utilizing Acceleration function: 10 s typical Space Efficient Packaging - 48-pin TSOP and 48-ball FBGA packages LOGIC DIAGRAM 21 A[20:0] CE# OE# WE# RESET# BYTE# DQ[14:0] DQ[15]/A[-1] WP#/ACC RY/BY# 15 Product Brief May 2001 HY29DS322/HY29DS323 GENERAL DESCRIPTION The HY29DS322/HY29DS323 (HY29DS32x) is a 32 Mbit, 2.0 volt-only CMOS Flash memory organized as 4,194,304 (4M) bytes or 2,097,152 (2M) words. The device is available in 48-pin TSOP and 48-ball FBGA packages. Word-wide data (x16) appears on DQ[15:0] and byte-wide (x8) data appears on DQ[7:0]. The HY29DS32x Flash memory array is organized into 71 sectors in two banks. Bank 1 contains eight 8 KByte boot/parameter sectors and 7 or 15 larger sectors of 64 KBytes each, depending on the version of the device. Bank 2 contains the rest of the memory array, organized as 56 or 48 sectors of 64 KBytes: Device programming is performed a byte/word at a time by executing the four-cycle Program Command write sequence. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Faster programming times can be achieved by placing the HY29DS32x in the Unlock Bypass mode, which requires only two write cycles to program data instead of four. The HY29DS32x's sector erase architecture allows any number of array sectors, in one or both banks, to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase Command sequence. This initiates an internal algorithm that automatically preprograms the sector before executing the erase operation. As during programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. Hardware Sector Group Protection optionally disables both program and erase operations in any combination of the sector groups, while Temporary Sector Group Unprotect, which requires a high voltage on one pin, allows in-system erasure and code changes in previously protected sector groups. Erase Suspend enables the user to put erase on hold in a bank for any period of time to read data from or program data to any sector in that bank that is not selected for erasure. True background erase can thus be achieved. Because the HY29DS32x features simultaneous read/write capability, there is no need to suspend to read from a sector located within a bank that does not contain sectors marked for erasure. The device is fully erased when shipped from the factory. Addresses and data needed for the programming and erase operations are internally latched during write cycles. The host system can detect completion of a program or erase operation by observing the RY/BY# pin or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. After a program or erase cycle has been completed, or after assertion of the RESET# pin (which terminates any operation in progress), the device is ready to read data or to accept another com PB May 01 Bank 1 Bank 2 8 x 8KB/4KW HY29DS322 56 x 64KB/32KW 7 x 64KB/32KW 8 x 8KB/4KW HY29DS323 48 x 64KB/32KW 15 x 64KB/32KW The device features simultaneous read/write operation, which allows the host system to invoke a program or erase operation in one bank and immediately and simultaneously read data from the other bank, except if that bank has any sectors marked for erasure, with zero latency. This releases the system from waiting for the completion of program or erase operations, thus improving overall system performance. The HY29DS32x can be programmed and erased in-system with a single 2.0 volt 10% VCC supply. Internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a higher voltage VPP power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as low as 100ns are offered for timing compatibility with the zero wait state requirements of high speed microprocessors. To eliminate bus contention, the HY29DS32x has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device is compatible with the JEDEC singlepower-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. 2 HY29DS322/HY29DS323 mand. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Secured Sector is an extra 64 Kbyte sector capable of being permanently locked at the factory or by customers. The Secured Indicator Bit (accessed via the Electronic ID mode) is permanently set to a 1 if the part is factory locked, and permanently set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The Secured Sector may store a secure, random 16-byte ESN (Electronic Serial Number), customer code programmed at the factory, or both. Customer Lockable parts may utilize the Secured Sector as bonus space, reading and writing like any other Flash sector, or may permanently lock their own code there. The WP#/ACC pin provides access to two functions. The Write Protect function provides a hardware method of protecting certain boot sectors without using a high voltage. The Accelerate function speeds up programming operations, and is intended primarily to allow faster manufacturing throughput. BLOCK DIAGRAM DQ[15:0] Two power-saving features are embodied in the HY29DS32x. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The host can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Common Flash Memory Interface (CFI) To make Flash memories interchangeable and to encourage adoption of new Flash technologies, major Flash memory suppliers developed a flexible method of identifying Flash memory sizes and configurations in which all necessary Flash device parameters are stored directly on the device. Parameters stored include memory size, byte/word configuration, sector configuration, necessary voltages and timing information. This allows one set of software drivers to identify and use a variety of different, current and future Flash products. The standard which details the software interface necessary to access the device to identify it and to determine its characteristics is the Common Flash Memory Interface (CFI) Specification. The HY29DS32x is fully compliant with this specification. A[20:0], A-1 STATE CONTROL COMMAND REGISTER ERASE VOLTAGE GENERATOR AND SECTOR SWITCHES CFI DATA MEMORY PROGRAM VOLTAGE GENERATOR Y-DECODER I/O CONTROL I/O BUFFERS WE# CE# OE# RESET# BYTE# CFI CONTROL DATA LATCH WP#/ACC TIMER A[20:0], A-1 ADDRESS LATCH RY/BY# Y-GATING 32 Mb FLASH MEMORY ARRAY (2 Banks, 71 Sectors) X-DECODER VCC DETECTOR 0.5 Mb FLASH Security Sector PB May 01 3 HY29DS322/HY29DS323 SIGNAL DESCRIPTIONS Name A[20:0] Type Inputs Description Address, active High. In word mode, these 21 inputs select one of 2,097,152 (2M) words within the array for read or write operations. In byte mode, these inputs are combined with the DQ[15]/A[-1] input (LSB) to select one of 4,194,304 (4M) bytes within the array for read or write operations. DQ[15]/A[-1], DQ[14:0] BY TE# CE# Data Bus, active High. In word mode, these pins provide a 16-bit data path Inputs/Outputs for read and write operations. In byte mode, DQ[7:0] provide an 8-bit data path Tri-state and DQ[15]/A[-1] is used as the LSB of the 22-bit byte address input. DQ[14:8] are unused and remain tri-stated in byte mode.. Input Input Byte Mode, active Low. Low selects byte mode, High selects word mode. Chip Enable, active Low. This input must be asserted to read data from or write data to the HY 29DS32x. When High, the data bus is tri-stated and the device is placed in the Standby mode. Output Enable, active Low. This input must be asserted for read operations and negated for write operations. When High, data outputs from the device are disabled and the data bus pins are placed in the high impedance state. Write Enable, active Low. Controls writing of commands or command sequences f or var ious device oper at ions. A w r it e oper at ion t akes place w hen WE# is asserted while CE# is also Low and OE# is High. Hardware Reset, active Low. Provides a hardware method of resetting the HY 29DS32x to the read array state. When the device is reset, it immediately terminates any operation in progress. The data bus is tri-stated and all read/write commands are ignored while the input is asserted. While RESET# is asserted the device will be in the Standby mode. Re a dy / Bus y St a t us . I nd ic a t e s w he t he r a w r it e o r e r a s e c o mma nd is in progress or has been completed. Valid after the rising edge of the final WE# pulse of a command sequence. Remains Low w hile t he device is act ively programming data or erasing, and goes High when it is ready to read array data. Write Protect, active Low/Accelerate (VHH). W r it e Pr ot ect Funct ion: Placing t his pin at VI L disables pr ogr am and er ase operations in two of the eight 8 KByte boot sectors. The affected sectors are sectors S0 and S1 in a bottom-boot device, or S69 and S70 in a top-boot device. If the pin is placed at VIH, the protection state of those two sectors reverts to w het her t hey w ere last set t o be prot ect ed or unprot ect ed using t he Sect or Group Protection and Unprotection capability of the HY 29DS32x. Accelerate Function: If VHH is applied to this input, the device enters the Unlock Bypass mode, t empor ar ily unpr ot ect s any pr ot ect ed sect or s, and uses t he higher voltage on the pin to reduce the time required for program operations. (The syst em w ould t hen use t he t w o-cycle program command sequence as required by the Unlock Bypass mode.) Removing VHH from the pin returns the device to normal operation. This pin must not be at VHH for operations other than accelerated programming, or device damage may result. Leaving the pin floating or unconnected may result in inconsistent device operation. 2-volt power supply. Power and signal ground. OE# Input WE# Input RESET# Input RY /BY # Output Open Drain WP#/ACC Input VCC VSS --- 4 PB May 01 HY29DS322/HY29DS323 PIN CONFIGURATIONS A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[19] A[20] WE# RESET# NC WP#/ACC RY/BY# A[18] A[17] A[7] A[6] A[5] A[4] A[3] A[2] A[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TSOP48 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A[16] BYTE# V SS DQ[15]/A[-1] DQ[7] DQ[14] DQ[6] DQ[13] DQ[5] DQ[12] DQ[4] VCC DQ[11] DQ[3] DQ[10] DQ[2] DQ[9] DQ[1] DQ[8] DQ[0] OE# V SS CE# A[0] 48-Ball FBGA - Top View, Balls Facing Down C7 A[13] C6 A[9] C5 WE# C4 D7 A[12] D6 A[8] D5 RESET# D4 E7 A[14] E6 A[10] E5 NC E4 F7 A[15] F6 A[11] F5 A[19] F4 A[20] F3 A[5] F2 A[1] G7 A[16] G6 DQ[7] G5 DQ[5] G4 DQ[2] G3 DQ[0] G2 A[0] H7 V IH H6 J7 DQ[15] J6 K7 V SS K6 DQ[6] K5 DQ[4] K4 DQ[14] DQ[13] H5 DQ[12] H4 DQ[10] H3 DQ[8] H2 CE# J5 V CC J4 R Y / B Y # W P # / A C C A[18] C3 A[7] C2 A[3] D3 A[17] D2 A[4] E3 A[6] E2 A[2] DQ[11] DQ[3] J3 DQ[9] J2 OE# K3 DQ[1] K2 V SS PB May 01 5 HY29DS322/HY29DS323 IMPORTANT NOTICE (c) 2001 by Hynix Semiconductor America Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Hynix Semiconductor Inc. or Hynix Semiconductor America Inc. (collectively "Hynix"). This document describes a product currently under design by Hynix. The information in this document is subject to change without notice. Hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. Hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. Memory Sales and Marketing Division Hynix Semiconductor Inc. 10 Fl., Hynix Youngdong Building 89, Daechi-dong Kangnam-gu Seoul, Korea Telephone: +82-2-580-5000 Fax: +82-2-3459-3990 http://www.hynix.com 6 Flash Memory Business Unit Hynix Semiconductor America Inc. 3101 North First Street San Jose, CA 95134 USA Telephone: (408) 232-8800 Fax: (408) 232-8805 http://www.us.hynix.com PB May 01 |
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